1. Field of the Invention
The invention relates to a method for fabricating a dielectric layer doped with nitrogen, and more particularly, to a method for fabricating a gate oxide layer doped with nitrogen uniformly.
2. Description of the Prior Art
In order to increase the integrity of a single wafer, semiconductor elements are made smaller and more compact. However, for higher performance, the thickness of a gate oxide layer of a complementary metal oxide (CMOS) device is decreased to maintain the capacitance between a gate and a channel. This is because the bigger the capacitance, the smaller the electric field within the gate oxide layer, and while the electric field is small, current leakage is prevented. For example, in a semiconductor process beyond 130 nm, an oxide gate layer smaller than 20 angstroms is required to achieve good performance.
Generally, silicon oxide is used as a gate oxide layer. However, thin layer of silicon oxide cannot meet the requirements of high dielectric constant, stable thermal properties, high breakdown voltage, and small current leakage. For example, leakage currents may occur in silicon oxide layers with thickness smaller than 50 angstroms due to electrons and holes tunneling through the energy barrier of the silicon oxide layer. To fix this shortcoming, nitrogen is doped into the silicon oxide layer so as to increase the dielectric constant of the silicon oxide layer. As a result, a gate oxide layer with the same capacitance and larger physical thickness, i.e. a gate oxide layer with the same equivalent oxide thickness (EOT), is formed.
In the prior art, there are at least two methods to dope nitrogen into a gate oxide layer. The first one is to thermally grow a gate oxide layer in a nitride ambiance, such as by a rapid thermal oxidation (RTO) process performed in nitrogen oxide ambiance, or by a thermal oxidation process performed in ammonia ambiance. Nevertheless, such a thermal growth process may lead to low nitrogen concentration in the oxide layer, or current leakage due to hydrogen diffusion into the oxide layer.
Another way to dope a gate oxide layer with nitrogen is by a plasma nitridation process, such as a single step decoupled plasma nitridation (DPN) process. In a DPN process, a plasma nitridation process and an annealing process are performed to form an oxide layer with an EOT smaller than 11 angstroms. The DPN process not only decreases the current leakage efficiently, but also offers a better barrier to boron, so as to facilitate the performance of a transistor.
However, uniformity of thickness and uniformity of nitrogen dopants in a gate oxide layer cannot be reached using a single step DPN process. More particularly, the nitrogen distribution is nonuniform around the center of the wafer. In addition, the average uniformity is not satisfying. Taking a 90 nm process as an example, gate oxide layer doping by a DPN process has nitrogen uniformity of about 8.1%. Since the nitrogen distribution is non-uniform, the capacitance, threshold voltage and other electric properties of a wafer are affected. Therefore the yield of the wafer may be decreased. As a result, a method to improve the uniformity of the nitrogen distribution in an gate oxide layer is required to increase the yield.